We are looking for a Senior Analog/Mixed Signal Engineer with 3-5 years of experience to design and implement critical circuit building blocks for next-generation AI compute chips at a fast-scaling semiconductor startup. You'll join a team that recently taped out its third chip and is now defining the architecture for multiple upcoming designs. This is a rare opportunity to work at the ground level of a new compute paradigm in a fast-moving startup environment where everyone gets their hands dirty.
What will you be doing?
- Designing analog and mixed-signal building blocks including ADCs, PLLs, band gaps, regulators, oscillators, high-speed dividers, and serializer/deserializers
- Owning block-level design across multiple chips, from architecture and schematic through layout and tape-out verification (DRC, ERC, LVS)
- Performing hands-on layout work as well as comprehensive simulations in Cadence (PEX, Monte-Carlo, Corner analysis)
- Supporting lab testing and validation of mixed-signal circuits using signal generators, spectrum analyzers, and oscilloscopes
- Collaborating cross-functionally with IC, systems, physics, and algorithms teams to bring sampling and compute units from concept to silicon
- Must have experience with analog and mixed signal blocks, such as comparators and PLLs
- CMOS background is essential; experience with FinFET or lower nodes is a plus
- 3-6 years of experience in analog/mixed-signal IC design using CMOS technology
- Multiple tape-out experiences, ideally in FinFET or 28nm/65nm nodes
- MS or PhD in Electrical Engineering focused on analog/mixed-signal
- Mixed-signal design experience (not purely analog-only background)
- Cadence simulation proficiency (PEX, Monte-Carlo, corner analysis)
- Willing to do unglamorous circuit work outside their specialty